Power semiconductor devices which include high-voltage field-effect transistor (HVFET) devices and other integrated circuits (ICs) that dissipate high power are well known in the semiconductor arts. Such power semiconductor devices are typically encapsulated within a package that is designed for assembly onto a printed circuit board (PCB). FIG. 1 is a side view of a typical prior art semiconductor package 100 that includes a body 110 and a plurality of leads 120 that extend outward from the sides of the body. Each of the leads is wider at the top as compared to the bottom. Where the width of leads 120 transition from the narrower bottom part to the wider top part, shoulders 126 are provided. The shoulders 126 of each of leads 120 typically rest on a top surface of the PCB (not shown) when the package is assembled. This provides a separation distance between a bottom surface 140 of package body 110 and the top surface of the PCB. Although this separation distance is useful when cleaning off the top surface of the PCB, this package design suffers from a number of drawbacks.
One of the drawbacks with the prior art semiconductor package of FIG. 1, is that the increased width at the top of leads 120 increases the overall size of the package. This occurs because leads 120 need to be separated by a minimum distance, referred to as a clearance distance, to meet certain electrical standards. Furthermore, any downward force applied to the top of package body 110 during the initial insertion into the PCB and/or during attachment of a heat sink is transferred to the shoulders of the leads. This can stress the leads and cause bending, breaking, or disconnecting of the leads (and/or lead wires) connected to the semiconductor die housed within the package body. In addition, such downward forces may also stress the package body causing delamination of the internal wiring connected to the semiconductor die within the package body.